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[SYCL] Flash Attention with XMX engine via oneDNN (#25222)
* [SYCL] F16 (default) Flash Attention with XMX engine via oneDNN graph API; Qwen3.6-27b-Q8_0 prefill speed up x1.21 at p=512 and x4.26 at p=80k * [SYCL] Address review on FA oneDNN path. Result: llama-bench---pp512; 32% increase with fa1; llama-perplexity---0.11% difference; tested model: mradermacher/Meta-Llama-3.1-8B-Instruct-Q8_0.gguf * PR-25222 revision v2: addressed audits * [SYCL] flash-attn oneDNN SDPA KV F16 rev 3.0: add BMG gate + multi-device sync. Narrow the scrope of this PR to Battlemage only (bmg; Xe2). Other archs (e.g., alchemist) fall back to existing FA kernel. When device_count >1, apply stream -> wait_and_throw(), validated working path for multi-gpu sync fix by @maxious. Co-authored-by: maxious <81432+maxious@users.noreply.github.com> * updated comment on bmg gate, noted the issue --------- Co-authored-by: scientist3 <scientist.3@users.noreply.github.com> Co-authored-by: hmscider <hmscider@users.noreply.github.com> Co-authored-by: maxious <81432+maxious@users.noreply.github.com>
This commit is contained in:
hmscider
co-authored by
scientist3
hmscider
maxious
scientist3
hmscider
maxious
parent
12127defda
commit
32b741c336
@@ -64,6 +64,7 @@ extern int g_ggml_sycl_enable_fusion;
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extern int g_ggml_sycl_prioritize_dmmv;
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extern int g_ggml_sycl_enable_flash_attention;
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extern int g_ggml_sycl_dev2dev_memcpy;
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extern int g_ggml_sycl_fa_onednn;
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#if defined(__clang__) && __has_builtin(__builtin_expect)
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@@ -0,0 +1,265 @@
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#include <cstdint>
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#include <cstdio>
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#include <cstring>
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#include <string>
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#include <unordered_map>
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#include <vector>
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#include "fattn-onednn.hpp"
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#include "fattn-tile.hpp"
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// set minimum query length to treat as prefill (32)
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#define GGML_SYCL_FA_ONEDNN_MIN_Q 32
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bool ggml_sycl_flash_attn_ext_onednn_supported(const ggml_tensor * dst) {
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#if !GGML_SYCL_DNNL
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GGML_UNUSED(dst);
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return false;
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#else
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if (!g_ggml_sycl_fa_onednn) {
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return false;
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}
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// Battlemage (Xe2) only, for now. On other Intel archs oneDNN's fused SDPA returns wrong results
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// for some shapes (e.g. head_dim=64 on Arc / xe_hpg) -- an oneDNN bug tracked upstream at
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// https://github.com/uxlfoundation/oneDNN/issues/5510. Remove this hardware limitation once that
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// is fixed; until then non-BMG archs fall back to the existing FA kernel.
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const gpu_arch arch = ggml_sycl_info().devices[ggml_sycl_get_device()].hw_info.arch;
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if (arch != gpu_arch::intel_gpu_bmg_g21 && arch != gpu_arch::intel_gpu_bmg_g31) {
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return false;
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}
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const ggml_tensor * Q = dst->src[0];
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const ggml_tensor * K = dst->src[1];
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const ggml_tensor * V = dst->src[2];
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const ggml_tensor * mask = dst->src[3];
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const ggml_tensor * sinks = dst->src[4];
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// gate for f16 KV only for now
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// need to implement quantized KV
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if (K->type != GGML_TYPE_F16 || V->type != GGML_TYPE_F16) {
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return false;
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}
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// gate for the following cases
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// 1. if the oneDNN graph Add node has no input --> skip
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// 2. types other than f16 need different logical_tensor declaration
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// 3. the mask must be shape [1, 1, q, seq]
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// 4. sinks: excludes attention sink (Xiao et al., 2024) that can't be modeled by oneDNN graph
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if (!mask || mask->type != GGML_TYPE_F16 || mask->ne[2] != 1 || mask->ne[3] != 1 || sinks) {
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return false;
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}
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float max_bias = 0.0f, logit_softcap = 0.0f;
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memcpy(&max_bias, (const float *) dst->op_params + 1, sizeof(float));
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memcpy(&logit_softcap, (const float *) dst->op_params + 2, sizeof(float));
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if (max_bias != 0.0f || logit_softcap != 0.0f) {
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return false;
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}
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// K and V must share head_dim: the SDPA graph uses a single `d` for both.
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const int64_t d = K->ne[0];
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if (V->ne[0] != d || Q->ne[3] != 1) {
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return false;
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}
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// GQA must divide evenly.
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if (K->ne[2] == 0 || Q->ne[2] % K->ne[2] != 0) {
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return false;
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}
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// Prefill only.
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if (Q->ne[1] < GGML_SYCL_FA_ONEDNN_MIN_Q) {
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return false;
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}
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return true;
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#endif
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}
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#if GGML_SYCL_DNNL
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#include "dnnl.hpp"
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#include "dnnl_sycl.hpp"
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#include "oneapi/dnnl/dnnl_graph.hpp" // graph API lives only under oneapi/dnnl/, not at the include root
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using namespace dnnl;
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using namespace dnnl::graph;
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// strided src (f16 or f32) -> contiguous f16 [ne0,ne1,ne2,ne3] (ne0 innermost). nb* are BYTE strides.
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template <typename src_t>
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static void cont_to_f16_sycl(const char * src, sycl::half * dst,
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int64_t ne0, int64_t ne1, int64_t ne2, int64_t ne3,
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size_t nb1, size_t nb2, size_t nb3, dpct::queue_ptr stream) {
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const int64_t n = ne0 * ne1 * ne2 * ne3;
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stream->parallel_for(sycl::range<1>(n), [=](sycl::id<1> ix) {
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const int64_t gid = ix[0];
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int64_t i = gid;
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const int64_t i0 = i % ne0; i /= ne0;
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const int64_t i1 = i % ne1; i /= ne1;
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const int64_t i2 = i % ne2; const int64_t i3 = i / ne2;
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const src_t * p = (const src_t *) (src + i1 * nb1 + i2 * nb2 + i3 * nb3) + i0;
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dst[gid] = (sycl::half) (*p);
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});
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}
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// oneDNN SDPA out (f16 contiguous [mb,H,q,d]) -> ggml dst (f32 [head_dim,H,n_tok,mb], contiguous).
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static void permute_sdpa_out_sycl(const sycl::half * out, float * dst,
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int64_t mb, int64_t H, int64_t q, int64_t d, dpct::queue_ptr stream) {
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const int64_t n = mb * H * q * d;
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stream->parallel_for(sycl::range<1>(n), [=](sycl::id<1> ix) {
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const int64_t gid = ix[0];
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int64_t i = gid;
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const int64_t e = i % d; i /= d;
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const int64_t t = i % q; i /= q;
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const int64_t h = i % H; const int64_t b = i / H;
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dst[e + h * d + t * d * H + b * d * H * q] = (float) out[gid];
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});
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}
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struct sdpa_partition {
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compiled_partition cp;
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std::vector<logical_tensor> ins;
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logical_tensor out;
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size_t id_q = 0, id_k = 0, id_v = 0, id_scale = 0, id_mask = 0;
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bool ok = false;
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};
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// Build + compile the contiguous-input GQA SDPA graph (MatMul->Divide->Add->SoftMax->MatMul), f32 out.
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// Mirrors the hardware-verified scratch/onednn_sdpa_probe.cpp build_gqa (partitions=1, sdp_primitive_kernel_t).
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static sdpa_partition build_sdpa(const engine & eng, int H, int Hkv, int q, int seq, int d) {
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using ltype = logical_tensor::layout_type;
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using dt = logical_tensor::data_type;
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using ldims = logical_tensor::dims;
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const dt fi = dt::f32, t = dt::f16;
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const int rep = H / Hkv;
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const ldims q_sz = {1, Hkv, rep, q, d}, kv_sz = {1, Hkv, 1, seq, d}, s_sz = {1, Hkv, rep, q, seq},
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sc = {1, 1, 1, 1, 1}, msk = {1, 1, 1, q, seq}, o_sz = {1, Hkv, rep, q, d};
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int64_t id = 0;
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sdpa_partition E;
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auto query = logical_tensor(id++, t, q_sz, ltype::strided);
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auto key = logical_tensor(id++, t, kv_sz, ltype::strided);
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auto score = logical_tensor(id++, fi, s_sz, ltype::strided);
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auto bmm1 = op(id++, op::kind::MatMul, "bmm1");
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bmm1.set_attr<bool>(op::attr::transpose_b, true); // key is [.., seq, d]
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bmm1.add_inputs({query, key}); bmm1.add_outputs({score});
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auto scale = logical_tensor(id++, t, sc, ltype::strided);
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auto scaled = logical_tensor(id++, fi, s_sz, ltype::strided);
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auto sdiv = op(id++, op::kind::Divide, "scale_div"); // score / (1/kq_scale) == score * kq_scale
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sdiv.add_inputs({score, scale}); sdiv.add_outputs({scaled});
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auto mask = logical_tensor(id++, t, msk, ltype::strided);
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auto masked = logical_tensor(id++, fi, s_sz, ltype::strided);
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auto madd = op(id++, op::kind::Add, "mask_add");
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madd.add_inputs({scaled, mask}); madd.add_outputs({masked});
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auto probs = logical_tensor(id++, t, s_sz, ltype::strided);
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auto smax = op(id++, op::kind::SoftMax, "softmax");
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smax.set_attr<int64_t>(op::attr::axis, -1);
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smax.set_attr<std::string>(op::attr::mode, "inf_as_zero");
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smax.add_inputs({masked}); smax.add_outputs({probs});
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auto value = logical_tensor(id++, t, kv_sz, ltype::strided);
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// f16 output is REQUIRED to hit sdp_primitive_kernel_t (the systolic micro-kernel); an f32 output
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// falls to larger_partition_kernel_t which materializes N^2 (confirmed: scratch/onednn_sdpa_kernel_probe.cpp).
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// converted to the f32 ggml dst in the permute below.
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auto output = logical_tensor(id++, t, o_sz, ltype::strided); // f16 contiguous [mb,Hkv,rep,q,d]
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auto bmm2 = op(id++, op::kind::MatMul, "bmm2");
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bmm2.add_inputs({probs, value}); bmm2.add_outputs({output});
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dnnl::graph::graph g(eng.get_kind());
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g.add_op(bmm1); g.add_op(sdiv); g.add_op(madd); g.add_op(smax); g.add_op(bmm2);
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g.finalize();
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auto parts = g.get_partitions();
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if (parts.size() != 1 || !parts[0].is_supported()) {
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return E; // ok stays false -> caller falls back to TILE
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}
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E.ins = parts[0].get_input_ports();
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E.out = parts[0].get_output_ports()[0];
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E.cp = parts[0].compile(E.ins, {E.out}, eng);
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E.out = E.cp.query_logical_tensor(E.out.get_id());
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E.id_q = query.get_id(); E.id_k = key.get_id(); E.id_v = value.get_id();
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E.id_scale = scale.get_id(); E.id_mask = mask.get_id();
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E.ok = true;
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return E;
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}
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void ggml_sycl_flash_attn_ext_onednn(ggml_backend_sycl_context & ctx, ggml_tensor * dst) try {
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const ggml_tensor * Q = dst->src[0];
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const ggml_tensor * K = dst->src[1];
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const ggml_tensor * V = dst->src[2];
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const ggml_tensor * mask = dst->src[3];
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const int64_t d = K->ne[0]; // head_dim
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const int64_t seq = K->ne[1]; // n_kv
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const int64_t Hkv = K->ne[2]; // n_head_kv
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const int64_t H = Q->ne[2]; // n_head
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const int64_t q = Q->ne[1]; // n_tok
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const int64_t mb = Q->ne[3]; // batch (== 1, gated)
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float kq_scale = 1.0f;
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memcpy(&kq_scale, (const float *) dst->op_params + 0, sizeof(float));
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dpct::queue_ptr stream = ctx.stream();
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dnnl::engine eng = ctx.engine_dnnl(stream);
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dnnl::stream strm = ctx.stream_dnnl(stream);
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// cont/cast inputs to contiguous f16 (head-major) -- the layout the fast systolic path wants.
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ggml_sycl_pool_alloc<sycl::half> Qf(ctx.pool(), (size_t) H * q * d);
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ggml_sycl_pool_alloc<sycl::half> Kf(ctx.pool(), (size_t) Hkv * seq * d);
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ggml_sycl_pool_alloc<sycl::half> Vf(ctx.pool(), (size_t) Hkv * seq * d);
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cont_to_f16_sycl<float> ((const char *) Q->data, Qf.get(), d, q, H, mb, Q->nb[1], Q->nb[2], Q->nb[3], stream);
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cont_to_f16_sycl<sycl::half>((const char *) K->data, Kf.get(), d, seq, Hkv, mb, K->nb[1], K->nb[2], K->nb[3], stream);
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cont_to_f16_sycl<sycl::half>((const char *) V->data, Vf.get(), d, seq, Hkv, mb, V->nb[1], V->nb[2], V->nb[3], stream);
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// divide-by-(1/scale) reproduces ggml's score *= kq_scale on the proven probe graph.
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const sycl::half scale_h = (sycl::half) (1.0f / kq_scale);
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ggml_sycl_pool_alloc<sycl::half> scbuf(ctx.pool(), 1);
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stream->memcpy(scbuf.get(), &scale_h, sizeof(sycl::half));
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ggml_sycl_pool_alloc<sycl::half> outf(ctx.pool(), (size_t) H * q * d); // f16 contiguous SDPA out [mb,H,q,d]
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// compile once per (device, shape), reuse across layers/calls.
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static std::unordered_map<std::string, sdpa_partition> cache;
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char keyb[96];
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snprintf(keyb, sizeof(keyb), "%d:%lld:%lld:%lld:%lld:%lld", ggml_sycl_get_device(),
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(long long) H, (long long) Hkv, (long long) q, (long long) seq, (long long) d);
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auto it = cache.find(keyb);
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if (it == cache.end()) {
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it = cache.emplace(keyb, build_sdpa(eng, (int) H, (int) Hkv, (int) q, (int) seq, (int) d)).first;
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}
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sdpa_partition & E = it->second;
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// _supported() is authoritative: if it accepted this op the partition must build.
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// A failure here is a gap in _supported() -- surface it, don't mask it with a fallback.
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GGML_ASSERT(E.ok && "oneDNN SDPA partition failed to build for a _supported() shape");
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auto id2ptr = [&](size_t r) -> void * {
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if (r == E.id_q) return Qf.get();
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if (r == E.id_k) return Kf.get();
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if (r == E.id_v) return Vf.get();
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if (r == E.id_scale) return scbuf.get();
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if (r == E.id_mask) return (void *) mask->data;
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return nullptr;
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};
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std::vector<tensor> ti;
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ti.reserve(E.ins.size());
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for (auto & lt : E.ins) {
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ti.emplace_back(lt, eng, id2ptr(lt.get_id()));
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}
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tensor to(E.out, eng, outf.get());
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E.cp.execute(strm, ti, {to});
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permute_sdpa_out_sycl(outf.get(), (float *) dst->data, mb, H, q, d, stream);
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// Single device: no sync is required, and actually PP perf is ~6% > wait_and_throw() (tested on llama-3.1-8b & qwen3.6-27b, both Q8_0, with Arc B70).
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// Any future multi-GPU refactor MUST re-measure this single-device path and keep the best
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// single-device PP speed. Otherwise (multiple devices/streams can race the reuse):
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if (ggml_sycl_info().device_count > 1) {
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// cont_to_f16 -> oneDNN execute -> permute is async on this stream, but the
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// pool_alloc*s above free their device buffers at host return. Without this wait the next
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// scheduler op re-acquires those bytes while the GPU is still computing the SDPA, turning
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// it into garbage and collapsing multi-turn output to a single repeated token ("GGGGG...").
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stream->wait_and_throw();
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}
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}
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catch (const std::exception & e) {
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// any oneDNN/SYCL failure is non-fatal: fall back to the existing kernel (strictly additive).
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GGML_LOG_WARN("%s: oneDNN SDPA failed (%s); falling back to TILE kernel\n", __func__, e.what());
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ggml_sycl_flash_attn_ext_tile(ctx, dst);
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}
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#endif // GGML_SYCL_DNNL
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@@ -0,0 +1,14 @@
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#ifndef GGML_SYCL_FATTN_ONEDNN_HPP
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#define GGML_SYCL_FATTN_ONEDNN_HPP
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#include "common.hpp"
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// Static-only check: fused-XMX oneDNN Graph SDPA path==flash-attn op
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// (f16 KV, no softcap/ALiBi, single stream, tuned head_dim, prefill-sized q.)
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bool ggml_sycl_flash_attn_ext_onednn_supported(const ggml_tensor * dst);
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// Run flash attention through oneDNN's fused xmx SDPA
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// execute the cached SDPA partition, write the f32 dst. Falls back to the TILE kernel on any failure.
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void ggml_sycl_flash_attn_ext_onednn(ggml_backend_sycl_context & ctx, ggml_tensor * dst);
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#endif // GGML_SYCL_FATTN_ONEDNN_HPP
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@@ -18,6 +18,7 @@
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#include "fattn-tile.hpp"
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#include "fattn-vec.hpp"
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#include "fattn.hpp"
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#include "fattn-onednn.hpp"
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#define FATTN_VEC_CASE(D, type_K, type_V) \
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@@ -96,6 +97,7 @@ static void ggml_sycl_flash_attn_ext_vec(ggml_backend_sycl_context & ctx, ggml_t
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enum best_fattn_kernel {
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BEST_FATTN_KERNEL_NONE = 0,
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BEST_FATTN_KERNEL_VEC = 100,
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BEST_FATTN_KERNEL_ONEDNN = 150, // added enum for onednn==150
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BEST_FATTN_KERNEL_TILE = 200,
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};
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@@ -189,7 +191,11 @@ static best_fattn_kernel ggml_sycl_get_best_fattn_kernel(const int device, const
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// For small batch sizes the vector kernel may be preferable over the kernels optimized for large batch sizes:
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const bool can_use_vector_kernel = Q->ne[0] <= 512 && Q->ne[0] % 64 == 0 && K->ne[1] % FATTN_KQ_STRIDE == 0;
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// Todo: Use the XMX kernel if possible:
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// Fused-XMX path: oneDNN Graph SDPA (flash attention). Strictly
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// additive -- taken only when statically supported, otherwise falls through to VEC/TILE below.
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if (ggml_sycl_flash_attn_ext_onednn_supported(dst)) {
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return BEST_FATTN_KERNEL_ONEDNN;
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}
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|
||||
// If there are no tensor cores available, use the generic tile kernel:
|
||||
if (can_use_vector_kernel) {
|
||||
@@ -213,6 +219,13 @@ void ggml_sycl_flash_attn_ext(ggml_backend_sycl_context & ctx, ggml_tensor * dst
|
||||
switch (ggml_sycl_get_best_fattn_kernel(ggml_sycl_get_device(), dst)) {
|
||||
case BEST_FATTN_KERNEL_NONE:
|
||||
GGML_ABORT("Not support Flash-Attention");
|
||||
case BEST_FATTN_KERNEL_ONEDNN:
|
||||
// guarded: ggml_sycl_flash_attn_ext_onednn() is only defined under GGML_SYCL_DNNL;
|
||||
// the reference must be compiled out here or the GGML_SYCL_DNNL=0 build fails to link.
|
||||
#if GGML_SYCL_DNNL
|
||||
ggml_sycl_flash_attn_ext_onednn(ctx, dst);
|
||||
#endif
|
||||
break;
|
||||
case BEST_FATTN_KERNEL_TILE:
|
||||
ggml_sycl_flash_attn_ext_tile(ctx, dst);
|
||||
break;
|
||||
|
||||
@@ -84,6 +84,7 @@ int g_ggml_sycl_debug = 0;
|
||||
int g_ggml_sycl_enable_optimize = 1;
|
||||
int g_ggml_sycl_enable_graph = 0;
|
||||
int g_ggml_sycl_enable_dnn = 1;
|
||||
int g_ggml_sycl_fa_onednn = 1;
|
||||
int g_ggml_sycl_enable_vmm = 1;
|
||||
int g_ggml_sycl_enable_fusion = 1;
|
||||
int g_ggml_sycl_prioritize_dmmv = 0;
|
||||
@@ -285,6 +286,7 @@ static void ggml_check_sycl() try {
|
||||
g_ggml_sycl_enable_optimize = ggml_sycl_get_env("GGML_SYCL_ENABLE_OPT", 1);
|
||||
g_ggml_sycl_enable_graph = ggml_sycl_get_env("GGML_SYCL_ENABLE_GRAPH", 0);
|
||||
g_ggml_sycl_enable_dnn = ggml_sycl_get_env("GGML_SYCL_ENABLE_DNN", 1);
|
||||
g_ggml_sycl_fa_onednn = ggml_sycl_get_env("GGML_SYCL_FA_ONEDNN", 1);
|
||||
g_ggml_sycl_enable_vmm = ggml_sycl_get_env("GGML_SYCL_ENABLE_VMM", 1);
|
||||
g_ggml_sycl_enable_fusion = ggml_sycl_get_env("GGML_SYCL_ENABLE_FUSION", 1);
|
||||
g_ggml_sycl_prioritize_dmmv = ggml_sycl_get_env("GGML_SYCL_PRIORITIZE_DMMV", 0);
|
||||
@@ -352,8 +354,10 @@ static void ggml_check_sycl() try {
|
||||
|
||||
#if defined(GGML_SYCL_DNNL)
|
||||
GGML_LOG_INFO(" GGML_SYCL_ENABLE_DNN: %d\n", g_ggml_sycl_enable_dnn);
|
||||
GGML_LOG_INFO(" GGML_SYCL_FA_ONEDNN: %d\n", g_ggml_sycl_fa_onednn);
|
||||
#else
|
||||
GGML_LOG_INFO(" GGML_SYCL_ENABLE_DNN: DNN disabled by compile flag\n");
|
||||
GGML_LOG_INFO(" GGML_SYCL_FA_ONEDNN: %d\n", g_ggml_sycl_fa_onednn);
|
||||
#endif
|
||||
#ifdef SYCL_FLASH_ATTN
|
||||
GGML_LOG_INFO(" GGML_SYCL_ENABLE_FLASH_ATTN: %d\n", g_ggml_sycl_enable_flash_attention);
|
||||
|
||||
Reference in New Issue
Block a user